library ieee;
use ieee.std_logic_1164.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use ieee.numeric_std.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity oled_controller is
    generic (
        -- cycle constants
        OLED_WIDTH  : integer := 96;
        OLED_HEIGHT : integer := 64;
    );
    port (
        clk : in std_logic;
        res : in std_logic;

        -- pmodoledrgb SPI signals
        -- chip select output to slave
        pmod_cs     : out std_logic;
        -- mosi output to slave
        pmod_mosi   : out std_logic;
        -- sck output to slave
        pmod_sck    : out std_logic;

        -- pmodoledrgb control signals
        -- data/command control signal
        -- specifies if incoming data is to be interpreted as data or as a command
        pmod_dc     : out std_logic;
        -- reset pin
        -- when low, initialization of chip is executed
        -- keep high during operation
        pmod_res    : out std_logic;
        -- enable supply voltage
        pmod_vccen  : out std_logic;
        -- enable pmod
        pmod_pmoden : out std_logic;
    );
end ssd_controller;

architecture Behavioral of oled_controller is
    -- type declarations
    type spi_state_t is (READY);

    -- subtype declarations

    -- state definitions
    constant INITIAL_SPI_STATE : spi_state_t := READY;
    signal state      : spi_state_t := INITIAL_SPI_STATE;
    signal state_next : spi_state_t := INITIAL_SPI_STATE;
begin

    -- toggle VCC supply for screen
    pmod_vccen <= '0' when res else '1';
    -- toggle GND supply for screen
    pmod_pmoden <= '0' when res else '1';

    sync : process (clk, res)
    begin
        if res = '1' then
            state <= INITIAL_SPI_STATE;
        elsif rising_edge(clk) then
            state <= state_next;
        end if;
    end process;

    async : process (all)
    begin
        -- default assignments
        state_next <= state;
        pmod_cs <= '0';
        pmod_mosi <= '0';
        pmod_sck <= '0';
        pmod_dc <= '0';
        pmod_res <= '0';

        case state is
            when READY =>
                -- do something
        end case;
    end process;

end Behavioral;
